1. Field of the Invention
This invention is related to the field of processors and, more particularly, to register addressing within processors.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
Unfortunately, the x86 architecture includes certain features which complicate design of compilers for the architecture. For example, it is sometimes desirable to manipulate a byte of information as a variable. The x86 architecture provides for byte addressability of some of its registers, but not all. Additionally, those registers which are byte addressable provide for byte addressing of both the least significant byte and the next to the least significant byte. These features complicate the compiler's mapping of byte variables to registers in several ways. For example, if the compiler has already assigned all of the byte addressable registers to other (multi-byte) variables and a byte variable is encountered, the compiler must rearrange register assignments to accommodate the byte variable in a byte addressable register, write the previously assigned variable to memory to assign the byte addressable register to the byte variable, or assign the byte variable to a non-byte addressable register (and thus eliminate the non-byte addressable register's use for a multi-byte variable). Alternatively, the compiler may reserve one or more of the byte addressable registers for allocation to byte variables. However, in this case, the registers may not be assigned to other variables if not enough byte variables are encountered. Furthermore, mapping multiple byte variables to the same multi-byte register (since the least significant and next to least significant bytes are both byte addressable) may complicate register assignment by requiring the compiler to manage both the register name and two subfields within the register for assignment to two different byte variables.